SH7760 Datasheet, PDF (932/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 25.1 shows a block diagram of the HAC.
HAC receiver
HAC_
SD_IN (0/1)
Shift register for slot 1
Shift register for slot 2
Data[19:0]
Data[19:0]
Shift register for slot 3
Data[19:0]
HAC_
Shift register for slot 4
Data[19:0]
BIT_CLK(0/1)
Control
signal
Request signal
for slots 3 & 4
Bit control signal
Internal bus interface
(Reception)
CSAR RX buffer
CSDR RX buffer
PCML RX buffer
PCMR RX buffer
DMA control
Data[31:0]
DMA request
Interrupt request
HAC_
SD_OUT(0/1)
HAC_SYNC(0/1)
HAC_RES
HAC transmitter
Shift register for slot 1
Shift register for slot 2
Shift register for slot 3
Shift register for slot 4
Data[19:0]
Data[19:0]
Data[19:0]
Data[19:0]
Control
signal
Internal bus interface
(Transmission)
CSAR TX buffer
CSDR TX buffer
PCML TX buffer
PCMR TX buffer
DMA control
Data[31:0]
DMA request
Interrupt request
Figure 25.1 Block Diagram
25.2 Input/Output Pins
Table 25.1 describes the HAC pin configuration.
Table 25.1 Pin Configuration
Name
HAC_BIT_CLK (0/1)
HAC_SD_IN (0/1)
HAC_SD_OUT (0/1)
HAC_SYNC (0/1)
HAC_RES
# of Pins
1
1
1
1
1
I/O
Input
Input
Output
Output
Output
Function
HAC serial data clock
HAC serial data incoming to Rx frame
HAC serial data outgoing from Tx frame
HAC frame sync
HAC reset (negative logic signal) (common to
channels 0 and 1)
Rev. 1.0, 02/03, page 882 of 1294