SH7760 Datasheet, PDF (336/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 10.14 8-Bit Off-Chip Device/Little-Endian Access and Data Alignment
Operation
Access
D31 to
Size Address No. D24
Byte n
1—
Word 2n
1—
2n+1 2 —
Long-
word
4n
4n+1
1—
2—
4n+2 3 —
4n+3 4 —
Quad- 8n
word
8n+1
1—
2—
8n+2 3 —
8n+3 4 —
8n+4 5 —
8n+5 6 —
8n+6 7 —
8n+7 8 —
Data Bus
D23 to
D16
D15 to D8D7 to D0 WE3,
DQM3
—
—
Data
7 to 0
—
—
Data
7 to 0
—
—
Data
15 to 8
—
—
Data
7 to 0
—
—
Data
15 to 8
—
—
Data
23 to 16
—
—
Data
31 to 24
—
—
Data
7 to 0
—
—
Data
15 to 8
—
—
Data
23 to 16
—
—
Data
31 to 24
—
—
Data
39 to 32
—
—
Data
47 to 40
—
—
Data
55 to 48
—
—
Data
63 to 56
Strobe Signals
WE2, WE1, WE0,
DQM2 DQM1 DQM0
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Rev. 1.0, 02/03, page 286 of 1294