SH7760 Datasheet, PDF (607/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

17.3.6 Serial Control Register (SCSCR)
SCSCR is a register used to enable/disable transmission/reception by SCIF, serial clock output,
interrupt requests, and to select transmission/reception clock source for the SCIF.
SCSCR can always be read from and written to by the CPU.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
- TIE RIE TE RE REIE - CKE1 CKE0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R R/W R/W
Bit
15 to 8
Bit Name
—
Initial Value R/W
All 0
R
7
TIE
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Transmit Interrupt Enable
Enables or disables transmit-FIFO-data-empty
interrupt (TXI) request generation when serial
transmit data is transferred from SCFTDR to
SCTSR, the number of data bytes in SCFTDR
falls to or below the transmit trigger set number,
and the TDFE flag in SCFSR is set to 1.
TXI interrupt requests can be cleared using the
following methods: Either by reading 1 from the
TDFE flag, writing transmit data exceeding the
transmit trigger set number to SCFTDR and then
clearing the TDFE flag to 0, or by clearing the
TIE bit to 0.
0: Transmit-FIFO-data-empty interrupt (TXI)
request disabled
1: Transmit-FIFO-data-empty interrupt (TXI)
request enabled
Rev. 1.0, 02/03, page 557 of 1294