SH7760 Datasheet, PDF (247/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(2) IRL Interrupts
• Source: The interrupt mask level bits (IMASK3 to IMASK0) setting in SR is smaller than the
IRL (3–0) level, and the BL bit in SR is 0 (accepted at instruction boundary).
• Transition address: VBR + H'0000 0600
• Transition operations:
The PC contents immediately after the instruction at which the interrupt is accepted are set in
SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR.
The code corresponding to the IRL (3–0) level is set in INTEVT. See table 9.7, for the
corresponding codes. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to
VBR + H'0600. The acceptance level is not set in the interrupt mask level bits (IMASK3 to
IMASK0) in SR. When the BL bit in SR is 1, the interrupt is masked. For details, see section
9, Interrupt Controller (INTC).
IRL()
{
SPC = PC;
SSR = SR;
SGR = R15;
INTEVT = H'0000 0200 ~ H'0000 03C0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0600;
}
Rev. 1.0, 02/03, page 197 of 1294