SH7760 Datasheet, PDF (423/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

11.3.4 DMA Channel Control Register (CHCR)
CHCR is a 32-bit readable/writable register that specifies the operating mode and transfer method
for each channel. Bits 31 to 28 and 27 to 24 are only valid when the source and destination
addresses are in the CS5 or CS6 space and the relevant space has been specified as a PCMCIA
interface space. In other cases, these bits should be cleared to 0.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSA2 SSA1 SSA0 STC DSA2 DSA1 DSA0 DTC -
-
-
- DS RL AM AL
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 TM TS2 TS1 TS0 CHSET IE TE DE
Initial value: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name Initial Value R/W Description
31
SSA2
0
30
SSA1
0
29
SSA0
0
R/W Source Address Space Attribute Specification
R/W _{These bits specify the space attribute for the}
R/W _{source address when accessing a PCMCIA}
interface area. These bits are only valid in the
case of page mapping to PCMCIA connected to
areas 5 and 6.
000: Reserved in PCMCIA access
001: Dynamic bus sizing I/O space
010: 8-bit I/O space
011: 16-bit I/O space
100: 8-bit common memory space
101: 16-bit common memory space
110: 8-bit attribute memory space
111: 16-bit attribute memory space
Rev. 1.0, 02/03, page 373 of 1294