SH7760 Datasheet, PDF (349/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 10.14 shows the SRAM write timing when DCKDR is set to 1/2.
CKIO
A25−A0
CS1
RD/WR
WEn
D31−D0
(write)
BS
DCK
BS2
TS1 T1 Tw Tw Tw T2 TH1 TH2
Figure 10.14 DCK, BS2, and CS1 Timing when Writing to SRAM Interface
(DCKDR = H'0002, A1RDH = 1 and A1H[1:0] = 10 in WCR3,
CSH[1:0] in WCR4 = 10, Three Wait Cycles)
Rev. 1.0, 02/03, page 299 of 1294