SH7760 Datasheet, PDF (352/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(2) Address Multiplexing
Address multiplexing is performed so that synchronous DRAM can be connected without off-
chip multiplexing circuitry in accordance with the address multiplexing bits AMXEXT and
AMX2 to AMX0 in MCR. Table 10.15 shows the relationship between the address
multiplexing bits and the bits output on the address pins. The address signals output on address
pins A25 to A18, A1, and A0 are not guaranteed.
A0, which serves as the LSB of the synchronous DRAM address pin, specifies the longword
address connected to this LSI. Therefore, be sure to first connect pin A0 of the synchronous
DRAM to pin A2 of this LSI, and then connect pin A1 to pin A3.
Table 10.15 Example of Correspondence between This LSI and Synchronous DRAM
Address Pins (32-Bit Bus Width, AMX2 to AMX0 = 000, AMXEXT = 0)
Address Pin of This LSI
Synchronous
DRAM Address
RAS Cycle CAS Cycle
Pin
Function
A13
A21
A21
A11
Select bank address BANK
A12
A20
H/L
A10
Address precharge setting
A11
A19
0
A9
Address
A10
A18
0
A8
A9
A17
A9
A7
A8
A16
A8
A6
A7
A15
A7
A5
A6
A14
A6
A4
A5
A13
A5
A3
A4
A12
A4
A2
A3
A11
A3
A1
A2
A10
A2
A0
A1
Not used Not used Not used
A0
Not used Not used Not used
Rev. 1.0, 02/03, page 302 of 1294