SH7760 Datasheet, PDF (565/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
7
ICPE1*¹
0
6
ICPE0*¹
0
R/W Input Capture Control
R/W These bits, provided in channel 2 only, specify
whether the input capture function is used, and
control enabling or disabling of interrupt generation
when the function is used.
When the input capture function is used, a data
transfer request is sent to the DMAC in the event of
input capture.
The CKEG bits specify whether the rising edge or
falling edge of the TCLK pin is used to set the
TCNT2 value in TCPR2.
The TCNT2 value is set in TCPR2 only when the
ICPF bit in TCR2 is 0. When the ICPF bit is 1,
TCPR2 is not set in the event of input capture.
When input capture occurs, a DMAC transfer
request is generated regardless of the value of the
ICPF bit. However, a new DMAC transfer request is
not generated until processing of the previous
request is finished.
00: Input capture function is not used.
01: Setting prohibited
10: Input capture function is used, but interrupt due
to input capture (TICPI2) is not enabled.
Data transfer request is sent to the DMAC in
the event of input capture.
11: Input capture function is used, and interrupt
due to input capture (TICPI2) is enabled.
Data transfer request is sent to the DMAC in
the event of input capture.
5
UNIE
0
R/W Underflow Interrupt Control
Controls enabling or disabling of interrupt
generation when the UNF status flag is set to 1,
indicating TCNT underflow.
0: Interrupt due to underflow (TUNI) is disabled
1: Interrupt due to underflow (TUNI) is enabled
4
CKEG1
0
3
CKEG0
0
R/W Clock Edge 1 and 0
R/W These bits select the external clock input edge
when an external clock is selected or the input
capture function is used.
00: Count/input capture register set on rising edge
01: Count/input capture register set on falling edge
1X: Count/input capture register set on both rising
and falling edges
Rev. 1.0, 02/03, page 515 of 1294