SH7760 Datasheet, PDF (365/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CKIO
Bank
Precharge-sel
Adress
CSn
RD/WR
RAS
CASS
DQMn
Tpr Tpc Tr Trw Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Trw1 Trw1
Row
H/L
Row
H/L
Row
c1
H/L
c5
D31-D0
(Write)
BS
CKE
DACKn
(SA: IO → memory)
c1 c2 c3 c4 c5 c6 c7 c8
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.25 Burst Write Timing (Different Row Addresses)
(8) Pipelined Access
When the RASD bit in MCR is set to 1, pipelined access is performed for faster access to
synchronous DRAM between an access by the CPU and an access by the DMAC or for
consecutive accesses by the DMAC. Since synchronous DRAM is internally divided into two
or four banks, after a READ or WRIT command is issued for one bank it is possible to issue a
PRE, ACTV, or other command during the CAS latency cycle, data latch cycle, or data write
cycle for shortening the access cycle.
When a read access is followed by another read access to the same row address, after a READ
command has been issued, another READ command is issued before the end of the data latch
cycle so that read data is on the data bus continuously. When an access is made to another row
address and a different bank, the PRE command or ACTV command can be issued during the
CAS latency cycle or data latch cycle. If there are consecutive access requests for different row
addresses in the same bank, the PRE command cannot be issued until one cycle before the last
data latch cycle. If a write access follows a read access, a PRE or ACTV command can be
Rev. 1.0, 02/03, page 315 of 1294