SH7760 Datasheet, PDF (772/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bits Bit Name Initial Value R/W Description
7
HCFS1 0
6
HCFS0 0
R/W Host Controller Functional State
R/W _{HCD determines whether HC has started to route}
SOF after having read the SF bit of
HcInterruptStatus. This bit can be changed by HC
only in the USB suspend state. HC can change from
the USB suspend state to the USB resume state
after having detected the resume signal from the
downstream port. In HC, USB suspend is entered
after the software reset like USB reset is entered
after the hardware reset. The former resets the root
hub.
00: USB reset state
01: USB resume state
10: USB operation state
11: USB suspend state
5
BLE
0
R/W Bulk List Enable
This bit is set to enable the processing of the bulk list
in the next frame. HC checks this bit when the
processing of the list has been determined. When
this bit is 0 (disabling), HCD can modify the list.
When HcBulkCurrentED indicates ED to be deleted,
HCD should increment the pointer by updating
HcBulkCurrentED before re-enabling the list
processing.
0: Bulk list processing is disabled in the next frame
1: Bulk list processing is enabled in the next frame
4
CLE
0
R/W Control List Enable
This bit is set to 1 to enable processing of the control
list in the next frame. When cleared to 0 by HCD, the
control list is not processed after the next SOF. HC
must check this bit whenever the list is to be
processed. When this bit is 0 (disabling), HCD can
modify the list. When HcControlCurrentED indicates
ED to be deleted, HCD should increment the pointer
by updating HcControlCurrentED before re-enabling
list processing.
0: Control list processing is disabled in the next
frame
1: Control list processing is enabled in the next frame
Rev. 1.0, 02/03, page 722 of 1294