SH7760 Datasheet, PDF (945/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

25.3.9 RX Status Register (HACRSR)
HACRSR is a 32-bit read/write register that indicates the status of the HAC RX controller.
Writing 0 to the bit will initialize it.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
PLR PRR
STARY STDRY _{FRQ FRQ}
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
PLR PRR
FOV FOV
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R R/W R/W R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
31 to 23 
Initial Value R/W*
All 0
R
22
STARY
0
R/W
21
STDRY
0
R/W
20
PLRFRQ 0
R/W
19
PRRFRQ 0
R/W
18 to 14 
All 0
R
13
PLRFOV 0
R/W
Description
Reserved
Always 0 for read and write.
Status Address Ready
0: HACCSAR (status address) is not ready.
1: HACCSAR (status address) is ready.
Status Data Ready
0: HACCSDR (status data) is not ready.
1: HACCSDR (status data) is ready.
PCML RX Request
0: PCML RX data is not ready.
1: PCML RX data is ready and must be read. In
DMA mode, reading HACPCML automatically
clears this bit to 0.
PCMR RX Request
0: PCMR RX data is not ready.
1: PCMR RX data is ready and must be read. In
DMA mode, reading HACPCMR automatically
clears this bit to 0.
Reserved
Always 0 for read and write.
PCML RX Overrun
0: No PCML RX data overrun has occurred.
1: PCML RX data overrun has occurred because
the HAC has received new data from slot 3
with PLRFRQ = 1.
Rev. 1.0, 02/03, page 895 of 1294