SH7760 Datasheet, PDF (284/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

With this LSI, various types of memory or PC cards can be connected to each of the seven
areas of off-chip address space as shown in table 10.2, and chip select signals (CS0 to CS6,
CE2A, CE2B) are output for each of these areas. CS0 is asserted when accessing area 0, and
CS6 when accessing area 6. When synchronous DRAM is connected to area 2 or 3, signals
such as RAS, CASS, RD/WR, and DQM are also asserted. When the PCMCIA interface is
selected for area 5 or 6, CE2A or CE2B is asserted in addition to CS5 or CS6 for the byte to be
accessed.
H'0000 0000
P0 and
U0 areas
256
P0 and
U0 areas
H'8000 0000
P1 area
H'A000 0000
P2 area
H'C000 0000
P3 area
H'E000 0000 _{Store queue area}
H'E400 0000
H'FFFF FFFF
P4 area
Physical address
space
(MMU off)
P1 area
P2 area
P3 area
Store queue area
P4 area
Virtual address
space
(MMU on)
Area 0 (CS0)
H'0000 0000
Area 1 (CS1)
H'0400 0000
Area 2 (CS2)
H'0800 0000
Area 3 (CS3)
H'0C00 0000
Area 4 (CS4)
H'1000 0000
Area 5 (CS5)
H'1400 0000
Area 6 (CS6)
H'1800 0000
Area 7 (reserved area) ^{H'1C00 0000}
H'1FFF FFFF
External memory
space
Notes: 1. When the MMU is off (MMUCR.AT = 0), the top 3 bits of the 32-bit address are ignored, and
memory is mapped onto a fixed 29-bit external address.
2. When the MMU is on (MMUCR.AT = 1), the P0, U0, P3, and store queue areas can be
mapped onto any external address using the TLB.
Figure 10.2 Correspondence between Virtual Address Space and Off-chip Memory Space
Rev. 1.0, 02/03, page 234 of 1294