SH7760 Datasheet, PDF (545/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

14.2.3 Clock Stop Register 00 (CLKSTP00)
CLKSTP00 is a 32-bit readable/writable register that controls the operating clock for peripheral
modules. The clock supply is stopped by writing 1 to the corresponding bit in CLKSTP00.
The clock supply is restarted by writing 1 to the corresponding bit in CLKSTPCLR00. Writing 0
to CLKSTP00 will not change the bit value.
Table 14.4 shows which module each bit is assigned to.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSTP CSTP CSTP CSTP CSTP CSTP CSTP CSTP CSTP CSTP _- CSTP CSTP _- CSTP CSTP
31 30 29 28 27 26 25 24 23 22
20 19
17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CSTP CSTP CSTP CSTP CSTP CSTP CSTP CSTP
15 14 13 12 11 10
9
8
-
-
-
-
-
-
-
CSTP
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Table 14.4 Bit Assignment of CLKSTP00 and CLKSTPCLR00
Bit
Bit
Bit
No. Bit Name Module No. Bit Name Module No. Bit Name Module
Bit
No. Bit Name Module
31 CSTP31 SSI(1) 23 CSTP23 MFI
15 CSTP15 HAC(0) 7 

30 CSTP30 SSI(0) 22 CSTP22 HSPI 14 CSTP14 ADC
6

29 CSTP29 SCIF(2) 21 

13 CSTP13 HCAN2(1) 5 

28 CSTP28 SCIF(1) 20 CSTP20 LCDC 12 CSTP12 HCAN2(0) 4 

27 CSTP27 SCIF(0) 19 CSTP19 USB 11 CSTP11 DMABRG 3 

26 CSTP26 I²C(1) 18 

10 CSTP10 GPIO
2

25 CSTP25 I²C(0) 17 CSTP17 CMT 9 CSTP9 MMCIF 1 

24 CSTP24 SIM
16 CSTP16 HAC(1) 8 CSTP8 DMAC
0 CSTP0 INTC
Rev. 1.0, 02/03, page 495 of 1294