SH7760 Datasheet, PDF (277/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

9.5.2 Multiple Interrupts
When handling multiple interrupts, the interrupt handling routine should include the following
procedures:
1. Branch to the interrupt handling routine of each interrupt source using the INTEVT value as an
offset to identify the interrupt source.
2. Clear the interrupt source in the corresponding interrupt handling routine.
3. Save SPC and SSR in the stack.
4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask level bits
(IMASK3 to IMASK0) in SR.
5. Write the actual processing.
6. Set the BL bit in SR to 1.
7. Restore SSR and SPC from memory.
8. Execute the RTE instruction.
When these procedures are followed in order, an interrupt of higher priority than the one being
handled can be accepted immediately after step 4. This enables the interrupt response time to be
shortened for urgent processing.
9.5.3 Interrupt Masking with MAI Bit
By setting the MAI bit to 1 in ICR, interrupts can be masked while the NMI pin is low,
irrespective of the BL and IMASK bits in SR.
• In normal operation and sleep mode
All interrupts are masked while the NMI pin is low. However, an NMI interrupt only is
generated by a transition at the NMI pin.
• In standby mode
All interrupts are masked while the NMI pin is low, and an NMI interrupt is not generated by a
transition at the NMI pin. Therefore, standby mode cannot be cleared by an NMI interrupt
while the MAI bit is set to 1.
Rev. 1.0, 02/03, page 227 of 1294