SH7760 Datasheet, PDF (513/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(1) USB Address Error Interrupt Request (DMABRGI0)
When a USB address error occurs with the UAE bit in DMABRGCR set to 1, the DMABRG
sets the UAF bit in DMABRGCR to 1 and outputs an interrupt request to the INTC.
(2) All Data Transfer End Interrupt Request (DMABRGI1)
• When all data transfer is completed on the receive side for channel 1 of the HAC or SSI with
the A1RXEE bit in DMABRGCR set to 1, the DMABRG sets the A1RXEF bit in
DMABRGCR to 1 and outputs an interrupt request to the INTC.
• When all data transfer is completed on the transmit side for channel 1 of the HAC or SSI with
the A1TXEE bit in DMABRGCR set to 1, the DMABRG sets the A1TXEF bit in
DMABRGCR to 1 and outputs an interrupt request to the INTC.
• When all data transfer is completed on the receive side for channel 0 of the HAC or SSI with
the A0RXEE bit in DMABRGCR set to 1, the A0RXEF bit in DMABRGCR is set to 1 and an
interrupt request is output to the INTC.
• When all data transfer is completed on the transmit side for channel 0 of the HAC or SSI with
the A0TXEE bit in DMABRGCR set to 1, the DMABRG sets the A0TXEF bit in
DMABRGCR to 1 and outputs an interrupt request to the INTC.
• When USB data transfer is completed with the UTE bit in DMABRGCR set to 1, the
DMABRG sets the UTF bit in DMABRGCR to 1 and outputs an interrupt request to the INTC.
(3) Half Data Transfer End Interrupt Request (DMABRGI2)
• When data transfer of half of the bytes specified in DMAARXTCR is completed on the receive
side for channel 1 of the HAC or SSI with the A1RXHE bit in DMABRGCR set to 1, the
DMABRG sets the A1RXHF bit in DMABRGCR to 1 and outputs an interrupt request to the
INTC.
• When data transfer of half of the bytes specified in DMAARXTCR is completed on the
transmit side for channel 1 of the HAC or SSI with the A1TXHE bit in DMABRGCR set to 1,
the A1TXHF bit in DMABRGCR is set to 1 and an interrupt request is output to the INTC.
• When data transfer of half of the bytes specified in DMAARXTCR is completed on the receive
side for channel 0 of the HAC or SSI with the A0RXHE bit in DMABRGCR set to 1, the
DMABRG sets the A0RXHF bit in DMABRGCR to 1 and outputs an interrupt request to the
INTC.
• When data transfer of half of the bytes specified in DMAARXTCR is completed on the
transmit side for channel 0 of the HAC or SSI with the A0TXHE bit in DMABRGCR set to 1,
the DMABRG sets the A0TXHF bit in DMABRGCR to 1 and outputs an interrupt request to
the INTC.
The DMABRG outputs three types of interrupt requests to the INTC: an all data transfer end
interrupt, a half data transfer end interrupt and an address error interrupt. To know which
interrupt the DMABRG has issued, read interrupt flag bits in DMABRGCR. An interrupt flag
bit that is set to 1 indicates the corresponding interrupt has been output.
Rev. 1.0, 02/03, page 463 of 1294