SH7760 Datasheet, PDF (515/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Section 12 Clock Pulse Generator (CPG)
This LSI incorporates a clock pulse generator (CPG) that generates a CPU clock (Ick), peripheral
clock (Pck), bus clock (Bck), and module clock (Fck).
The CPG generates the clocks supplied inside the processor and performs power-down mode
control.
12.1 Features
The CPG has the following features.
• Six clock modes
Any of six clock operating modes can be selected, with different division ratio combinations of
the CPU clock, bus clock, and peripheral clock after a power-on reset.
• Five clocks
The CPG can generate individually the CPU clock (Ick) used by the CPU, FPU, caches, and
TLB, the peripheral clock (Pck) used by the peripheral modules, the bus clock (Bck) used by
the external bus interface, the module clock (Fck), and the DCK clock (DCK).
• Frequency change function
The PLL circuits and a frequency divider in the CPG enable the CPU clock, bus clock,
peripheral clock, module clock, and DCK clock frequencies to be changed independently.
Frequency changes are performed by software in accordance with the settings in FRQCR,
MCKCR, and DCKDR.
• PLL on/off control
Power consumption can be reduced by stopping the PLL circuits during low-frequency
operation.
• Power-down mode control
It is possible to stop the clock in sleep mode, deep sleep mode, hardware standby mode, and
software standby mode, and to stop specific modules with the module standby function.
Rev. 1.0, 02/03, page 465 of 1294