SH7760 Datasheet, PDF (556/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

14.3.7 Hardware Standby Mode Timing
Figure 14.12 shows the timing of the signals of the respective pins in hardware standby mode.
The CA pin level must be kept low while in hardware standby mode.
After setting the RESET pin level low, the clock starts when the CA pin level is switched to high.
CKIO
CA
RESET
STATUS
Normal*^1,*²
Standby*³ Undefined Reset*⁴
0–10 Bcyc*⁵
Waiting for end of bus cycle
0–10 Bcyc*⁵
Notes:
1. Same in sleep and reset.
2. Normal
3. Standby
4. Reset
5. Bcyc
: LL (STATUS1 is low and STATUS0 is low)
: LH (STATUS1 is low and STATUS0 is high)
: HH (STATUS1 is high and STATUS0 is high)
: Bus clock cycle
Figure 14.12 Hardware Standby Mode Timing
(When CA = Low in Normal Operation)
Rev. 1.0, 02/03, page 506 of 1294