SH7760 Datasheet, PDF (188/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 7.3 Store Queue Features
Item
Capacity
Addresses
Write
Write-back
Access right
Store Queues
32 bytes × 2
H’E000 0000 to H’E3FF FFFF
Store instruction (1-cycle write)
Prefetch instruction (PREF instruction)
MMU is off: Determined by SQMD bit in MMUCR
MMU is on: Determined by PR for each page
Rev. 1.0, 02/03, page 138 of 1294