SH7760 Datasheet, PDF (764/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

When an underflow or overflow error condition is met, the CHNO[1:0] and SWNO bits can be
used to recover the SSI module to a known status. When an underflow or overflow occurs, the
host CPU can read the number of channels and the number of system words to determine what
point the serial audio stream has reached. In the transmitter case, the host CPU can skip forward
through the data it wants to transmit until it finds the sample data that matches what the SSI
module is expecting to transmit next, and so resynchronize with the audio data stream. In the
receiver case, the host CPU can skip forward storing null sample data until it is ready to store the
sample data that the SSI module is indicating that it will receive next to ensure consistency of the
number of received data, and so resynchronize with the audio data stream.
20.4.7 Serial Clock Control
This function is used to control and select which clock is used for the serial bus interface.
If the serial clock direction is set to input (SCKD = 0), the SSI module is in clock slave mode, then
the bit clock that is used in the shift register is derived from the SSI_SCK pin.
If the serial clock direction is set to output (SCKD = 1), the SSI Module is in clock master mode,
and the shift register uses the bit clock derived from the HAC_BIT_CLK input pin or its clock
divided. This input clock is then divided by the ratio in the serial oversampling clock division ratio
(CKDV) bit in SSICR and used as the bit clock in the shift register.
In either case, the SSI_SCK pin output is the same as the bit clock.
20.5 Usage Note
20.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation
If an overflow occurs during receive DMA operation, the module must be reactivated. If an
overflow occurs, recover the module according to the following procedure.
1. Ensure an overflow occurs through an overflow error interrupt or overflow error status flag
(the OIRQ bit in SSISR).
2. Terminate the DMA by writing 1 to the RDS bit in DMAACR. At this time, confirm the DMA
is terminated by reading in the RDS bit (0 can be read).
3. Disable the DMA in the SSI module to halt its operation by writing 0 to the EN bit and
DMEN bit in SSICR.
4. Confirm the remaining number of the DMA by reading the DMAARXTCNT to reset the start
address of the DMA and number of transfers (MDAARXDAR/DMAARXTCR).
5. Clear the overflow status flag by writing 0 to the OIRQ bit.
6. Reactivate the DMAC by writing 1 to the RDE bit in DMAACR.
7. Reactivate the module by enabling the SSI module and DMA again.
Rev. 1.0, 02/03, page 714 of 1294