SH7760 Datasheet, PDF (657/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
7 TIE
6 RIE
5 TE
Initial
Value R/W
0
R/W
0
R/W
0
R/W
Description
Transmit Interrupt Enable
Enables or disables transmit data empty interrupt (SIMTXI)
requests when serial transmit data is transferred from SITDR
to SITSR, and the TDRE flag in SISSR is set to 1.
0: Disables transmit data empty interrupt (SIMTXI)
requests*
1: Enables transmit data empty interrupt (SIMTXI)
requests
Note: * SIMTXI can be canceled by clearing either the TDRE
flag or TIE to 0.
Receive interrupt enable
Enables or disables receive data full interrupt (SIMRXI)
requests, and transmit/receive error interrupt (SIMERI)
requests due to parity errors, overrun errors, and error signal
status, when serial receive data is transferred from SIRSR to
SIRDR, and the RDRF flag in SISSR register is set to 1.
0: Disables receive data full interrupt (SIMRXI) requests
and transmit/receive error interrupt (SIMERI) requests*¹*²
1: Enables receive data full interrupt (SIMRXI) requests
and transmit/receive error interrupt (SIMERI) requests*²
Notes *1. SIMRXI and SIMERI interrupt requests can be
canceled by clearing the RDRF flag or the PER,
ORER or ERS flag or the RIE bit to 0.
*2. Wait error interrupt (SIMERI) requests are
enabled and disabled using the WAIT_IE bit in
SISCR.
Transmit Enable
Enables/disables serial transmission operations.
0: Disables transmission*¹
1: Enables transmission*²
Notes: *1.The TDRE flag in SISSR register is fixed at 1.
*2. In this state, if transmit data is written to SITDR,
the transmission operation is started. Before
setting the TE bit to 1, SISMR and SISCMR must
always be set to determine the transmission
format.
Rev. 1.0,02/03, page 607 of 1294