SH7760 Datasheet, PDF (846/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
15, 11,
10
Bit Name

Initial Value R/W
All 1
R
14 to IMR14 to All 1
R/W
12, 9 to IMR12,
0
IMR9 to
IMR0
Description
Reserved
This bit is always. Writing a 1 to this bit has no
effect. This bit is always read as 0.
Masks interrupt sources corresponding to IRR14
to IRR12, IRR9 to IRR0. When the bit is set, the
interrupt is masked, however, the CANIRR bit
setting is retained.
0: Corresponding CANIRR bit is not masked (IRQ
is generated for interrupt conditions).
1: Corresponding interrupt of CANIRR bit is
masked.
22.5.6 Transmit Error Counter and Receive Error Counter (CANTECREC)
CANTECREC is 16 bit read/(write) register and consists of the transmit error counter (TEC) and
receive error counter (REC) that function as a counter indicating the number of transmit/receive
message errors on the CAN interface. The counter value is stipulated in CAN Specification
Version 2.0, Robert Bosch GmbH, 1991 and Implementation Guide for the CAN Protocol, CAN
Specification 2.0 Addendum, CAN In Automation, Erlangen, Germany. In the normal mode, this
register is read-only and can only be modified by the CAN interface. This register can be cleared
by a Reset request (MCR0) or Bus off.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit
Bit Name Initial Value R/W Description
15 to 8 TEC7 to All 0
TEC0
R/W* Transmit error counter
7 to 0 REC7 to All 0
REC0
R/W* Receive error counter
Note: * It is possible to write the value only in test mode with MCR15 = MCR14 = 1.
Rev. 1.0, 02/03, page 796 of 1294