SH7760 Datasheet, PDF (778/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bits
Bit Name Initial Value R/W Description
3
RD
0
R/W Resume Detected
HC sets this bit to 1 when detecting the transmission
of a resume signal by a USB device. This bit is not
set when HCD sets USB resume state.
0: A USB device is not asserting a resume signal
1: A USB device is asserting a resume signal
2
SF
0
R/W Start of Frame
HC sets this bit to 1 when each frame is started and
after the HccaFrameNumber is updated. HC
simultaneously generates the SOF token.
0: Frame is not started or HccaFrameNumber is not
updated
1: Frame is started and HccaFrameNumber is
updated
1
WDH
0
R/W Writeback Done Head
HC sets this bit to 1 immediately after writing
HcDoneHead to HccaDoneHead. HccaDoneHead is
not updated until this bit is cleared. HCD should clear
this bit only after the content of HccaDoneHead has
been stored.
0: HccaDoneHead is retained
1: The value in HcDoneHead is written to
HccaDonehead
0
SO
0
R/W Scheduling Overrun
HC sets this bit to 1 when the USB schedule has
overrun in the current frame after
HccaFrameNumber is updated. Scheduling overrun
also increments the SOC bit in HcCommandStatus.
0: The USB schedule has not overrun in the current
frame
1: The USB schedule has overrun in the current
frame
21.3.5 Interrupt Enable Register (HcInterruptEnable)
Each enable bit in HcInterruptEnable corresponds to the related hardware interrupt bit in
HcInterruptStatus. A hardware interrupt is generated when bits in HcInterruptStatus are set to1,
the corresponding bits in HcInterruptEnable are set to 1, and HcInterruptEnable.MIE = 1.
Writing 1 to a bit in this register sets the corresponding bit to 1, while writing 0 does not clear the
bit to 0 but leaves it unchanged. Reading this register will return the current value of this register.
Rev. 1.0, 02/03, page 728 of 1294