SH7760 Datasheet, PDF (745/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

20.3.3 Transmit Data Register (SSITDR)
SSITDR is a 32-bit register that stores data to be transmitted.
Data written to SSITDR is transferred to the shift register as it is required for transmission. If the
data word length is less than 32 bits then its alignment should be as defined by the PDTA control
bit.
Reading this register will return the data in the buffer.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R
RRRR
R
R
R
R RR
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R
RRRR
R
R
R
R RR
R
20.3.4 Receive Data Register (SSIRDR)
SSIRDR is a 32-bit register that stores the received data.
Data in SSIRDR is transferred from the shift register as each data word is received. If the data
word length is less than 32 bits then its alignment should be as defined by the PDTA control bit in
SSICR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R
RRRR
R
R
R
R RR
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R
RRRR
R
R
R
R RR
R
Rev. 1.0, 02/03, page 695 of 1294