SH7760 Datasheet, PDF (867/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

22.6.4 Message Reception Sequence
The diagram below shows the message receive sequence.
HCAN2
End of arbitration Field
Idle
End of frame
CAN bus
Valid CAN-ID received
N=N-1
Loop (N=31(15) ; N > 0 ; N=N-1)
Compare ID with
Mailbox[N] + LAFM[N]
(if MBC is set to receive)
ID
No
matched?
No
N=0? ^Yes
Valid CAN frame received
Check MBC/
LAFM/CAN-ID
Incorrect
Correct
Yes
Store mailbox-number[N]
and go back to the idle state
RXPR[N]
(RFPR[N]) already
set?
No
Yes
Overwrite
MSG overwrite
or overrun?
(NMC)
Overrun
• Store message by
overwriting
• Set CANUMSR
• Set IRR9 (if MBIMR[N]=0)
• Generate interrupt signal
(if IMR9=0)
interrupt signal
• Reject message
• Set CANUMSR
• Set IRR9 (if MBIMR[N]=0)
• Generate interrupt signal
(if IMR9=0)
• Store message
• Set RXPR[N] (RFPR[N])
• Set IRR1
(IRR2) (if MBIMR[N]=0)
• Generate interrupt signal
(if IMR1(IMR2)=0)
interrupt signal
interrupt signal
Read IRR1=0
Read RXPR[N]=0
Write a 1 to RXPR[N]
Read Mailbox[N]
Read RXPR[N]=1
Yes
IRR1 set to 1? ^No
Read IRR
CPU received interrupt
Note: * Please confirm CANUMSR[N] = 0 when NMC[N] = 1
Figure 22.8 Message Receive Sequence
Rev. 1.0, 02/03, page 817 of 1294