SH7760 Datasheet, PDF (225/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

8.4.1 Exception Event Register (EXPEVT)
EXPEVT consists of a 12-bit exception code. The exception code set in EXPEVT is that for a
reset or general exception event. The exception code is set automatically by hardware when an
exception occurs. EXPEVT can also be modified by software.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
Initial value: 0
0
0
0
*
R/W: R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name Initial Value R/W Description
31 to 12 
All 0
R
Reserved
These bits are always read as 0, and the write
value should always be 0.
11 to 0
*
R/W 12-bit exception code
Note: * H'000 is set in a power-on reset, and H'020 in a manual reset.
8.4.2 Interrupt Event Register (INTEVT)
INTEVT consists of a 14-bit interrupt exception code. The interrupt exception code is set
automatically by hardware when an exception occurs. INTEVT can also be modified by software.
Bit: 31
-
Initial value: 0
R/W: R
Bit: 15
-
Initial value: 0
R/W: R
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 14 
13 to 0
Initial Value R/W
All 0
R

R/W
Description
Reserved
These bits are always read as 0, and the write
value should always be 0.
14-bit interrupt exception code
Rev. 1.0, 02/03, page 175 of 1294