SH7760 Datasheet, PDF (1036/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

27.5 Interface (Basic)
This section describes the 8-bit parallel interface using the MFI. The MFI interface enables access
to the 68 and 80 series. Access via the MFI is complete within a fixed time.
27.5.1 68-Series 8-Bit Parallel Interface
Figure 27.4 shows the basic read/write sequence for the 68-series 8-bit parallel interface. MFI
access is limited to the period during which the MFI-E/WR signal is driven high and the MFI-CS
signal is simultaneously driven low. During this period, a write operation is performed with the
MFI-RW/RD signal driven low; a read operation is performed with this signal driven high. The
MFI-RS signal indicates whether this is normal access or index/status register access; the low
level indicates normal access, and the high level indicates an index/status register access.
For details of the timing, refer to section 33, the AC Characteristics.
MFI-CS
MFI-RS
MFI-E/WR
MFI-RW/RD
MFI-D15 - MFI-D0
Write cycle
Read cycle
WT_D
RD_D
WT_D: Write data
RD_D: Read data
Figure 27.4 Basic Timing for the MFI 68-Series Interface
Rev. 1.0, 02/03, page 986 of 1294