SH7760 Datasheet, PDF (514/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

11.7 Usage Notes
1. When modifying SAR, DAR, DMATCR, and CHCR, first clear the DE bit for the relevant
channel.
2. Inputting an NMI interrupt with the DMAC not operating sets the NMIF bit in DMAOR.
• When DMA transfer is not correctly performed, take the following actions:
Read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in CHCR, and DMATCR
on this LSI. If the NMIF bit was set before the transfer, the DMATCR indicates the transfer
count that has been specified. If the NMIF bit was set during the transfer, when the DE bit is 1
and the TE bit is 0 in CHCR, the DMATCR indicates the number of transfers remaining.
Also, the next addresses to be accessed can be found by reading SAR and DAR.
If the AE bit has been set, an address error has occurred. Check the settings in CHCR, SAR,
and DAR.
3. Check that DMA transfer is not in progress before making a transition to module standby state,
standby mode, or deep sleep mode.
Either check CHCR.TE = 1, or set DMAOR.DME = 0 to terminate DMA transfer. Setting
DMAOR.DME = 0 stops the transfer on the completion of the DMA bus cycle currently being
performed. Note, therefore, that transfer may not end immediately, depending on the transfer
data size. DMA operation is not guaranteed if module standby state, standby mode, or deep
sleep mode is entered without confirming that DMA transfer has ended.
4. Do not specify a DMAC, cache, BSC, or UBC control register as the DMAC transfer source or
destination.
5. When activating the DMAC, make the SAR, DAR, and DMATCR settings for the relevant
channel before setting the DE bit to 1 in CHCR, or make the register settings with the DE bit in
CHCR cleared to 0, then set the DE bit to 1. It does not matter whether setting of the DME bit
in DMAOR to 1 is carried out first or last. To operate the relevant channel, the DME and DE
bits must both be set to 1. The DMAC may not operate normally if the SAR, DAR, and
DMATCR settings are not made (with the exception of the unused register in single address
mode).
6. After the DMATCR count reaches 0 and DMA transfer ends successfully, always write 0 to
DMATCR even when executing the maximum number of transfers on the same channel.
7. When using falling edge detection for external requests, hold the external request pin high to
make DMAC settings.
8. When using the DMAC in single address mode, specify an external address as the address.
Specifying an on-chip peripheral module address causes an address error and stops transfers on
all channels.
Rev. 1.0, 02/03, page 464 of 1294