SH7760 Datasheet, PDF (358/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
Tr Trw Tc1 Tc2 Tc3 Tc4 Trw1 Trw1 Tpc
Row
Row
H/L
Row
c1
D31–D0
(write)
c1
BS
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.19 Basic Timing for Synchronous DRAM Single Write
Rev. 1.0, 02/03, page 308 of 1294