SH7760 Datasheet, PDF (971/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

• CMDR5
Bit: 7
Initial value: 0
R/W: R
6
5
4
3
CRC
0
0
RR
0
0
RR
2
1
0
End
0
0
0
R
R
R
Bit
Bit Name
7 to 1 CRC
Initial
Value
All 0
0
End
0
R/W Description
R
These bits are always read as 0. The write value
should always be 0.
R
This bit is always read as 0. The write value should
always be 0.
26.3.6 Response Registers 0 to 16 (RSPR0 to RSPR16)
RSPR0 to RSPR16 are command response registers, which are seventeen 8-bit registers.
The number of command response bytes differs according to the command. The number of
command response bytes can be specified by RSPTYR in the MMCIF. The command response is
shifted-in from bit 0 in RSPR16, and shifted to the number of command response bytes × 8 bits.
Table 26.5 summarizes the correspondence between the number of command response bytes and
valid RSPR register.
Rev. 1.0, 02/03, page 921 of 1294