SH7760 Datasheet, PDF (310/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W
Description
15
A3W2 1
14
A3W1 1
13
A3W0 1
R/W Area 3 Wait Control
R/W
These bits specify the number of wait cycles to be
R/W
inserted for area 3. An external wait input is available for
SRAM and MPX interfaces and is not available for
synchronous DRAM interface. For the case where an
MPX interface setting is made, see table 10.7.
• When SRAM interface is in use:
Inserted wait cycles
RDY pin
000: 0
Disabled
001: 1
Enabled
010: 2
Enabled
011: 3
Enabled
100: 6
Enabled
101: 9
Enabled
110: 12
Enabled
111: 15
Enabled
• When synchronous DRAM interface is in use*¹:
Synchronous DRAM CAS latency cycles
000:
001:
Setting prohibited
1*²
010: 2
011: 3
100: 4*²
101: 5*²
110: Setting prohibited
111: Setting prohibited
12

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.0, 02/03, page 260 of 1294