SH7760 Datasheet, PDF (550/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(1) In Reset
(a) Power-on reset
CKIO
RESET
PLL stabilization
time
STATUS
Normal*¹
Reset*²
0–5 Bcyc*³
0–30 Bcyc*³
Notes: 1. Normal
2. Reset
3. Bcyc
: LL (STATUS1 is low and STATUS0 is low)
: HH (STATUS1 is high and STATUS0 is high)
: Bus clock cycle
Normal*¹
Figure 14.1 STATUS Output in Power-On Reset
(b) Manual reset
CKIO
RESET _(High)
MRESET*¹
STATUS
Normal*²
Reset *³
Normal *²
≥ 0 Bcyc *^1,*⁴
0–30 Bcyc *⁴
Notes:
1. In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting
until the end of the currently executing bus cycle
2. Normal
3. Reset
4. Bcyc
:LL (STATUS1 is low and STATUS0 is low)
:HH (STATUS1 is high and STATUS0 is high)
: Bus clock cycle
Figure 14.2 STATUS Output in Manual Reset
Rev. 1.0, 02/03, page 500 of 1294