SH7760 Datasheet, PDF (1271/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CKIO
Bank
Precharge-sel
Tc1
Tc2
Tc3
Tc4/Td1
Td2
Td3
Td4
Td5
Td6
Td7
Td8
t_AD
t_AD
t_AD
H/L
H/L
Address
CSn
RD/WR
RAS
CASS
DQMn
D31-D0
(read)
c1
t_CSD
t_RWD
t_RASD
t_CASD2 t_CASD2
t_DQMD
BS
CKE
DACKn
(SA: IO memory)
c5
t_CSD
t_RWD
t_RASD
t_DQMD
t_RDS
t_RDH
c1
c2
c3
c4
c5
c6
c7
c8
t_BSD
t_BSD
t_DACD
t_DACD
NOTES: IO : Dack device
SA : Single address DMA transfer
DA : Dual address DMA transfer
DACK set to active-high
Figure 33.29 Synchronous DRAM Normal Read Bus Cycle: READ Command,
Burst (CAS Latency=3)
Rev. 1.0, 02/03, page 1221 of 1294