SH7760 Datasheet, PDF (704/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

19.3.10 Receive/Transmit Data Registers (ICRXD/ICTXD)
Reading from or writing to this register means accessing different physical internal registers.
When data is to be transmitted, data in the shift register is loaded to TXD. After data has been
received into the shift register from the I²C bus, data is loaded to RXD.
• Receive Data Register (ICRXD) (Single Buffer Mode)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
-
RXD
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 8 
Initial Value R/W
All 0
R
7 to 0 RXD
All 0
R/W
Description
Reserved
These bits are always read as 0, and the write
value should always be 0.
Read Receive Data
Data received by master or slave.
• Transmit Data Register (ICTXD) (Single Buffer Mode)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
-
TXD
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 8 
Initial Value R/W
All 0
R
7 to 0 TXD
All 0
R/W
Description
Reserved
These bits are always read as 0, and the write
value should always be 0.
Write Transmit Data
Data transmitted by master or slave.
When the FIFO buffer is selected by the SDBS bit of ICSCR or the MDBS bit of ICMCR, the
operation is as follows:
Rev. 1.0, 02/03, page 654 of 1294