SH7760 Datasheet, PDF (359/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(7) RAS Down Mode
The synchronous DRAM bank function is used to support high-speed accesses to the same row
address. When the RASD bit in MCR is 1, the read/write commands perform access using
commands without auto-precharge (READ, WRIT). In this case, precharging is not performed
when the access ends. When accessing the same row address in the same bank, it is possible to
issue the READ or WRIT command immediately without issuing an ACTV command in the
same way as in the DRAM RAS down state. Since the synchronous DRAM is internally
divided into two or four banks, one row address in each bank can be activated. If the next
access is to a different row address, a PRE command is first issued to precharge the relevant
bank, and then when precharging is completed, the access is performed by issuing an ACTV
command followed by a READ or WRIT command. If this is followed by an access to a
different row address, the access time will be longer because of the precharging performed
after the access request is issued.
In a write, when auto-precharge is performed, a command cannot be issued for a period of
Trwl + Tpc cycles after issuance of the WRITA command. When RAS down mode is used,
READ or WRIT commands can be issued successively if the row address is the same. The
number of cycles can thus be reduced by Trwl + Tpc cycles for each write. Bits TPC2 to TPC0
in MCR are used to determine the number of cycles between issuance of the PRE command
and the ACTV command.
There is a limit on the time t_RAS that each bank can be kept in the active state. If execution of a
program cannot guarantee that this time value can be observed so that an access to a different
row address occurs by a cache miss, auto-refresh must be set and a refresh cycle must be used
that is no more than the maximum value of t_RAS. This makes it possible to observe the
restrictions on the maximum active state time for each bank. If auto-refresh is not used,
measures must be taken in the program to ensure that the banks do not remain active for longer
than the prescribed time.
A burst read cycle without auto-precharge is shown in figure 10.20, a burst read cycle for the
same row address in figure 10.21, and a burst read cycle for different row addresses in figure
10.22. Similarly, a burst write cycle without auto-precharge is shown in figure 10.23, a burst
write cycle for the same row address in figure 10.24, and a burst write cycle for different row
addresses in figure 10.25.
When synchronous DRAM is read, there is a 2-cycle latency for the DQMn signal that
specifies the bytes. As a result, when the READ command is issued in figure 10.20, if the Tc
cycle is executed immediately, the DQMn signal is not specified for the cycle Td1 data output.
Therefore, the CAS latency should not be set to 1.
Rev. 1.0, 02/03, page 309 of 1294