SH7760 Datasheet, PDF (589/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

16.4.5 16-Bit Timer: Output Compare
When operating in output compare mode, the 16-bit counters will be free-running using the clocks
defined by the timer clock control bits. Bits 15 to 0 in the channel time register are compared with
the 16-bit counter for that channel. When the values become equal, the output will be inverted
from its current state (i.e. toggled), and the interrupt compare bit will be set. The counter will then
be reset to H'0000 and will begin counting again. Each time a match on the counter occurs, the
output will be toggled. The counters will retain their values or can be cleared to H'0000 by
disabling the timer enable bits.
Common between channels
IRQ
CMT_CTR
FRT =
Count
Clock generation
16-bit counter
Peripheral bus
Channel time register
Preload
Figure 16.7 16-Bit Timer Mode: Output Compare
Rev. 1.0, 02/03, page 539 of 1294