SH7760 Datasheet, PDF (942/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

25.3.7 TX Status Register (HACTSR)
HACTSR is a 32-bit read/write register that indicates the status of the HAC TX controller. Writing
0 to the bit will initialize it.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMD CMD PLT PRT _-
-
-
-
-
-
-
-
-
-
-
-
AMT DMT FRQ FRQ
Initial value: 1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
PLT PRT
FUN FUN
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R
R
R
R
R
R
R
R
Bit
Bit Name
31
CMDAMT
30
CMDDMT
29
PLTFRQ
28
PRTFRQ
27 to 10 
Initial Value R/W*²
1
R/W
1
R/W
1
R/W
1
R/W
All 0
R
Description
Command Address Empty
0: CSAR Tx buffer contains untransmitted data.
1: CSAR Tx buffer is empty and ready to store
data.*¹
Restrictions related to the CMDAMT bit are
described in 25.5.5. For details of HAC
initialization steps, see the operational flow in
25.5.6.
Command Data Empty
0: CSDR Tx buffer contains untransmitted data.
1: CSDR Tx buffer is empty and ready to store
data. *¹
PCML TX Request
0: PCML Tx buffer contains untransmitted data.
1: PCML TX buffer is empty and needs to store
data. In DMA mode, writing to HACPCML will
automatically clear this bit to 0.
PCMR TX Request
0: PCMR Tx buffer contains untransmitted data.
1: PCMR TX buffer is empty and needs to store
data. In DMA mode, writing to HACPCMR will
automatically clear this bit to 0.
Reserved
Always 0 for read and write.
Rev. 1.0, 02/03, page 892 of 1294