SH7760 Datasheet, PDF (852/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

• CANTXACK0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0
_15
_14
_13
_12
_11
_10
_9
_8
_7
_6
_5
_4
_3
_2
_1
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R
Bit
Bit Name
Initial Value R/W Description
15 to 1 TXACK0[15:1] All 0
R/W*
Notifies that requested transmission of the
corresponding Mailbox has been finished
successfully. Bits 15 to 1 correspond to
Mailboxes 15 to 1 respectively.
0: Clearing condition: Write a 1 to this bit.
1: The corresponding Mailbox has
successfully transmitted messages
(Data or Remote Frame).
Setting condition: Completion of message
transmission for the corresponding Mailbox
0

0
R
Reserved
This bit is always 0 as this Mailbox is receive-
only. Writing a 1 to this bit has no effect. This
bit is always read as 0.
Note: * Only a write of 1 only is allowed to clear the bit.
22.5.10 Abort Acknowledge Registers 1 and 0 (CANABACK1, CANABACK0)
The CANABACK registers are two 16-bit read/conditionally-write registers that are used to signal
to the CPU that a mailbox transmission has been aborted as per its each request. When an abort
has succeeded, the HCAN2 sets the corresponding bit in CANABACK. The host CPU may clear
the Abort Acknowledge bit by writing a 1 to the corresponding bit. Writing a 0 has no effect. A
CANABACK bits position is set by the HCAN2 to acknowledge that a CANTXPR bit has been
cleared by the corresponding CANTXCR bit.
• CANABACK1
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1
_15
_14
_13
_12
_11
_10
_9
_8
_7
_6
_5
_4
_3
_2
_1
_0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Rev. 1.0, 02/03, page 802 of 1294