SH7760 Datasheet, PDF (687/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Section 19 Hitachi I²C Interface
This LSI contains an on-chip 2-channel I²C bus interface compatible with the Philips I²C bus (Inter
IC Bus) interface. It should be noted, however, the register structure used to control the I²C bus
differs from that of the Philips implementation.
19.1 Features
• Supports the Philips I²C bus interface.
• Multi-master capability.
• 7- or 10-bit address compatible master.
• 7-bit slave address.
• Fast mode compatible.
• Adaptable to a wide range of system clock frequencies.
• Supports 16-stage FIFO buffer mode.
Figure 19.1 shows a connection example for the I²C bus interface.
Rev. 1.0, 02/03, page 637 of 1294