SH7760 Datasheet, PDF (261/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
6 to 0 —
All 0
—
Reserved
These bits are always read as 0.The write value
should always be 0.
Note: * 1 when NMI pin input is high, 0 when low.
9.3.4 Interrupt Source Registers 00, 04 (INTREQ00, INTREQ04)
INTREQ00 and INTREQ04 are 32-bit read-only registers that indicate the origin of the interrupt
request sent to the INTC. The states of the bits in these registers are not affected by masking of the
corresponding interrupts by the settings in INTPRI00 and INTPRI04.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
31 to 0
Initial Value R/W
All 0
R
Description
Interrupt Requests 31 to 0
Each bit indicates that there is an interrupt
request relevant to that bit. For the
correspondence between the bits and interrupt
sources, see table 9.5.
0: There is no interrupt request that corresponds
to this bit
1: There is an interrupt request that corresponds
to this bit.
Rev. 1.0, 02/03, page 211 of 1294