SH7760 Datasheet, PDF (834/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

22.5.2 General Status Register (CANGSR)
CANGSR is a 16-bit read-only register that indicates the status of the HCAN2.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
- GSR5 GSR4 GSR3 GSR2 GSR1 GSR0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
R/W: R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 6 —
Initial Value R/W
All 0
—
5
GSR5
0
R
4
GSR4
0
R
3
GSR3
1
R
Description
Reserved
The write value should always be 0. The read
value is not guaranteed.
Error Passive Status
Indicates that the CAN Interface is Error Passive
or not. This bit will be set as soon as the HCAN2
enters the Error Passive state and is cleared
when the module returns to the Error Active state
(This means that GSR5 will stay high during the
Error Passive and Bus Off). Consequently, to find
out the accurate state, both GSR5 and GSR0
must be considered.
0: HCAN2 is not Error Passive.
Setting condition: HCAN2 is in Error Active
state.
1: HCAN is Error Passive (if GSR.0 = 0)
Setting condition: TEC ≥ 128 or REC ≥
128
Halt/Sleep Status
Indicates whether the CAN Interface is in the
Halt/Sleep state or not.
0: HCAN2 is not in the Halt state or Sleep state.
1: HCAN2 is in the Halt mode (if MCR1 = 1)
or Sleep mode (if MCR5 = 1).
Setting condition: when MCR1 is set and the
CAN bus is in intermission or idle state.
Reset Status
Indicates whether the CAN interface is in the
Reset state (Configuration mode) or not.
0: Normal operating state
Setting condition: After the HCAN2 internal
Reset
1: Reset state (Configuration mode)
Rev. 1.0, 02/03, page 784 of 1294