SH7760 Datasheet, PDF (1075/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

29.4.3 Scan Mode
In scan mode, analog inputs for a maximum of four specified channels are converted in succession
as shown below.
1. When the ADST bit in ADCSR is set to 1 by software or an external trigger input, A/D
conversion starts with the first channel (AN0).
2. A/D conversion for the first channel starts. When multiple channels are selected, the input
signal for the second channel (AN1) is converted after the A/D conversion for the first channel
ends.
3. When conversion of each channel ends, the conversion results are transmitted to the ADDRA
to ADDRD data register that corresponds to the channel.
4. When conversion of all selected channel ends, the ADF bit of ADCSR is set to 1. If the ADIE
bit is also set to 1, an ADI interrupt is generated at this time.
5. While the ADST bit is set to 1, it is not automatically cleared, but steps 2 to 4 above are
repeated. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter
becomes idle.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described
below. Figure 29.4 shows a timing diagram for this example.
1. Select scan mode as the operating mode (MDS1 = 1 and MDS0 = 1) and AN0 to AN2 as the
input channels (CH1 = 1 and CH0 = 0). Then start A/D conversion (ADST = 1).
2. A/D conversion of the first channel (AN0) starts. When the A/D conversion ends, the result is
transferred into ADDRA. Next, the second channel (AN1) is selected automatically and A/D
conversion starts.
3. Conversion proceeds in the same way up to the third channel (AN2).
4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF bit is set to 1,
the first channel (AN0) is selected again, and A/D conversion is consecutively performed. (In
multi mode, A/D conversion ends when the selected channels have been cycled through.
However, in scan mode, after the selected channels have been cycled through, A/D conversion
starts again from the first channel and is consecutively repeated.)
If the DMASL bit is cleared to 0 and the ADIE bit is set to 1 at this time, an ADI interrupt is
generated after A/D conversion ends.
5. While the ADST bit is set to 1, steps 2 to 4 above are repeated. When the ADST bit is cleared
to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again
from the first channel (AN0).
Rev. 1.0, 02/03, page 1025 of 1294