SH7760 Datasheet, PDF (465/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CKIO
A26–A0
CSn
D31–D0
RD
WE
DACK
Transfer source
address
Data read cycle
(1st cycle)
Transfer destination
address
Data write cycle
(2nd cycle)
Transfer from external memory space to external memory space
Figure 11.9 Example of Transfer Timing in Dual Address Mode
(2) Bus Modes
There are two bus modes: cycle steal mode and burst mode. The bus mode is selected for each
channel with the TM bit in CHCR0 to CHCR7.
• Cycle Steal Mode
In cycle steal mode, the DMAC releases the bus to the CPU at the end of each transfer-unit (8-
bit, 16-bit, 32-bit, 64-bit, or 32-byte) transfer. When the next transfer request is issued, the
DMAC reacquires the bus from the CPU and carries out another transfer-unit transfer. At the
end of this transfer, the bus is again given to the CPU. This is repeated until the transfer end
condition is satisfied.
In cycle steal mode, areas for transfer has no limitation by the settings of transfer request
source, transfer source, and transfer destination.
Figure 11.10 shows an example of DMA transfer timing in cycle steal mode. The following
transfer conditions are used in this example:
• Dual address mode
• DREQ level detection
Rev. 1.0, 02/03, page 415 of 1294