SH7760 Datasheet, PDF (761/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

20.4.6 Receive Operation
As with transmission the reception can be controlled in one of two ways: either DMA or an
interrupt driven.
Figures 20.23 and 20.24 show the flow of operation.
When disabling the SSI module, the SSI clock* must be supplied continuously until the module
enters in the idle state, which is indicated by the IIRQ bit.
Note: * SCKD = 0: Clock input through the SSI_SCK pin
SCKD = 1: Clock input through the HAC_BIT_CLK pin
Rev. 1.0, 02/03, page 711 of 1294