SH7760 Datasheet, PDF (192/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

7.2.1 Cache Control Register (CCR)
CCR selects the cache operating mode, whether all cache entries are disabled, and the cache write
mode.
CCR can be accessed in longwords from H'FF00 001C in the P4 area and from H'1F00 001C in
area 7. CCR modifications must only be made by a program in the non-cached P2 area. After CCR
is updated, an instruction that performs data access to the P0, P1, P3, or U0 area should be located
at least four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1,
P3, or U0 area should be located at least eight instructions after the CCR update instruction.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EMODE -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10
IIX -
-
- ICI -
Initial value: 0
0
0
0
0
0
R/W: R/W R
R
R R/W R
9
8
7
6
5
4
3
2
1
0
- ICE OIX - ORA - OCI CB WT OCE
0
0
0
0
0
0
0
0
0
0
R R/W R/W R R/W R R/W R/W R/W R/W
Bit
Bit Name
31
EMODE
30 to 16 
15
IIX
14 to 12 
11
ICI
Initial Value R/W
0
R/W
All 0
R
0
R/W
All 0
R
0
R/W
Description
Double-Size Cache Mode Bit
This bit selects whether double-size cache mode
is used or not. Do not write to this bit while cache
is being used.
0: Cache direct mapping mode
1: Double-size cache mode
Reserved
These bits are always read as 0. The write value
should always be 0.
IC Index Enable Bit
0: Effective address bits [12:5] used for IC entry
selection
1: Effective address bits [25] and [11:5] used for
IC entry selection
Reserved
These bits are always read as 0. The write value
should always be 0.
IC Invalidation Bit
When 1 is written to this bit, the V bits of all IC
entries are cleared to 0. This bit is always read
as 0.
Rev. 1.0, 02/03, page 142 of 1294