SH7760 Datasheet, PDF (494/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

6. Specify CHCRn.DM [1:0] and SM [1:0] = 00 in the corresponding channel, and CHCRn.RS
[3:0] = 0111.
7. Setting CHCRn.TE = 0 for the corresponding channel carries out DMA transfer for requests
that were retained in DMAC.
8. Confirm that the corresponding channel DMARCR.REXn = 0.
Note:
When DMA transfer ends while DMAOR.AE = 1 or DMAOR.NMIF = 1, requests may be cleared
even if DMARCR.REXn = 1. In that case, see “1. End of transfer with DMAOR.AE = 1” and “2.
End of transfer with DMAOR.NMIF = 1” in (2) Conditions for Ending Transfer Simultaneously
on All Channels of this section.
11.4.7 Interrupt-Request Codes
When the number of transfers specified in DMATCR has been finished and the IE bit in CHCR is
set to 1, a transfer-end interrupt request can be sent to the CPU from each channel. Table 11.10
lists the interrupt-request codes that are associated with these DMAC interrupts.
Table 11.10 DMAC Interrupt-Request Codes
Interrupt Source
Description
INTEVT Code Priority
DMTE0
CH0 transfer-end interrupt*
H'640
High
DMTE1
CH1 transfer-end interrupt
H'660
DMTE2
CH2 transfer-end interrupt
H'680
DMTE3
CH3 transfer-end interrupt
H'6A0
DMTE4
CH4 transfer-end interrupt
H'780
DMTE5
CH5 transfer-end interrupt
H'7A0
DMTE6
CH6 transfer-end interrupt
H'7C0
DMTE7
CH7 transfer-end interrupt
H'7E0
DMAE
Address error interrupt
H'6C0
DMABRGI0
USB address error interrupt
H’A80
DMABRGI1
All data transfer end interrupt
H’AA0
DMABRGI2
Half data transfer end interrupt H’AC0
Low
Note: * A CH0 transfer-end interrupt cannot be generated when the DMABRG in DMABRG mode
is used.
Rev. 1.0, 02/03, page 444 of 1294