SH7760 Datasheet, PDF (1270/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 33.28 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ
Commands, Burst (RCD[1:0]=01, TPC[2:0]=001, CAS Latency=3)
Rev. 1.0, 02/03, page 1220 of 1294