SH7760 Datasheet, PDF (376/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(b) Burst Write
Figure 10.32 is the timing chart for a burst-write operation with a burst length of 8. In this
LSI, a burst write takes place when a copy-back of the cache or a 32-byte transfer of data
by the DMAC occurs. In a burst-write operation, a WRITA command that performs auto
precharging is issued during the Tc1 cycle after the Tr cycle where the ACTV command is
output. During the write cycle, the write data is output simultaneously with the write
command. For a write command with an auto precharge, since precharging of the relevant
bank in the synchronous DRAM is performed after completion of the write command, no
new command for the same bank can be issued until precharging has been completed. As a
result, besides the precharge waiting cycle Tpc in read access, Trwl cycles are added to
provide waiting time until precharging starts after the write command has been issued, and
these Trwl cycles delay the issuing of new commands to the same bank. Bits TRWL2 to
TRWL0 in MCR can be used to select the number of Trwl cycles. The 32-byte boundary
data is written in wraparound mode.
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
Tr Trw Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Trw1 Trw1 Tpc
Row
Row
H/L
Row
c1
D31–D0
(write)
c1 c2 c3 c4 c5 c6 c7 c8
BS
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.32 Basic Timing of a Burst Write to Synchronous DRAM
Rev. 1.0, 02/03, page 326 of 1294