SH7760 Datasheet, PDF (259/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 9.4 Interrupt Request Sources and INTPRI00 to INTPRI0C*¹
Bits
Register 31 to 28
27 to 24
23 to 20
19 to 16
15 to 12 11 to 8
7 to 4
3 to 0
INTPRI00 IRQ4*³
IRQ5*³
IRQ6
IRQ7
Reserved*² Reserved*² Reserved*² Reserved*²
INTPRI04 HCAN2(0) HCAN2(1) SSI(0)
SSI(1)
HAC(0)
HAC(1)
I²C(0)
I²C(1)
INTPRI08 USB
LCDC
DMABRG SCIF(0)
SCIF(1)
SCIF(2)
SIM
HSPI
INTPRI0C Reserved*² Reserved*² MMCIF
Reserved*² MFI
Reserved*² ADC
CMT
Notes: 1. As shown in table 9.4, eight peripheral modules are assigned to each register. Setting a
value from H'F (1111) to H'0 (0000) in each of the 4-bit groups configures interrupt
priority level for each group. Setting H'F designates priority level 15 (the highest level),
and setting H'0 designates priority level 0 (requests are masked).
2. Reserved: These bits are always read as 0. The write value should always be 0.
3. To enable an IRQ4 or IRQ5 interrupt in software standby mode, setting must be made
in this register as well as in IPRC. The same value must be set in both registers. Note
that software standby mode cannot be exited by an IRQ6 or IRQ7 interrupt.
9.3.3 Interrupt Control Register (ICR)
ICR sets the input signal detection mode for external interrupt input pin NMI and indicates the
input signal level at the NMI pin.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
NMIL MAI -
-
-
- NMIB NMIE IRLM -
-
-
-
-
-
-
Initial value: 0/1* 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W -
-
-
- R/W R/W R/W -
-
-
-
-
-
-
Bit
Bit Name Initial Value R/W Description
15
NMIL
0/1*
R
NMI Input Level
Sets the level of the signal input at the NMI pin.
This bit can be read to determine the NMI pin
level. It cannot be modified.
0: NMI pin input level is low
1: NMI pin input level is high
Rev. 1.0, 02/03, page 209 of 1294