SH7760 Datasheet, PDF (460/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 11.5 shows the changes in priority levels when transfer requests are issued simultaneously
for channels 0 and 3, and channel 1 generates a transfer request during a transfer on channel 0. The
operation of the DMAC in this case is as follows.
1. Transfer requests are issued simultaneously for channels 0 and 3.
2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed
first (channel 3 is on transfer standby).
3. A transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on
transfer standby).
4. At the end of the channel 0 transfer, channel 0 shifts to the lowest priority level.
5. At this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer is
started (channel 3 is on transfer standby).
6. At the end of the channel 1 transfer, channel 1 shifts to the lowest priority level.
7. The channel 3 transfer is started.
8. At the end of the channel 3 transfer, the channel 3 and channel 2 priority levels are lowered,
giving channel 3 the lowest priority.
Rev. 1.0, 02/03, page 410 of 1294