SH7760 Datasheet, PDF (407/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CKIO
A25−A0
CSm
CSn
T1
T2
Twait
T1
T2
Twait
T1
T2
BS
RD/WR
RD
D31−D0
Read from Area m space
Read from Area n space
Write to Area n space
Wait cycle insertion between
access cycles specified for Area m
Wait cycle insertion between
access cycles specified for Area n
Figure 10.60 Wait Cycles between Access Cycles
10.6.10 Bus Arbitration
This LSI provides a bus arbitration function that allows an off-chip device to control the bus in
response to a bus request.
In normal operation, this LSI controls the bus, and it releases the bus to transfer the right to access
the bus when an off-chip device issues a bus request. In the description below, an off-chip device
that issues bus requests is referred to as a slave.
This LSI has two internal bus masters: the CPU and DMAC. When synchronous DRAM is
connected and refresh control is performed, the refresh request serves as the third bus master. Bus
requests from off-chip devices are also added when this LSI is in master mode. If requests occur
simultaneously, the priority from highest to lowest is based on the following order: bus request
from an off-chip device, the refresh request, the DMAC, and the CPU.
To prevent malfunctions of connected devices when the right to access the bus is transferred from
master to slave, all bus control signals are negated before the bus is released. When the right of
access to the bus is received, bus control signals switch from the negated level to start driving the
bus. Since signals are driven at the same level by the master and slave transferring the right to
access the bus, output buffer collisions can be avoided.
Rev. 1.0, 02/03, page 357 of 1294